AN805 vishay siliconix document number: 70649 january 1997 www.vishay.com faxback 408-970-5600 1 pwm optimized power mosfets for low-voltage dc/dc conversion designers of low-voltage dc-to-dc converters have two main concerns: reducing size and reducing losses. as a way of reducing size, designers are increasing switching frequencies. but the result has been reduced converter efficiency. to minimize losses, mosfet manufacturers have generally focused on lowering on-resistance. but the results have not been optimal for dc-to-dc conversion designs, since gate charge and switching speed issues have been largely ignored. the dominant losses associated with mosfets were once conduction losses, but this is no longer the case. vishay siliconix's new family of pwm optimized mosfets has been designed to give the highest efficiency available for a given on-resistance in switching applications such as dc-to-dc conversion. these new devices provide a very low gate charge per unit of on-resistance, in addition to fast switching times. the result is reduced gate drive and crossover losses, allowing designers of dc-to-dc converters to simultaneously reduce the design footprint and increase efficiency. mosfet losses a simplistic model of power loss in a mosfet used in a dc-to-dc converter (figure 1) can be calculated if we know the rms, the current through the mosfet, the duty cycle, the gate voltage, and the r ds(on) of the mosfet. this model can then be used to compare the efficiency of designs using vishay siliconix's new pwm optimized mosfets versus conventional and low-threshold power mosfets. the equation that defines the losses associated only with on-resistance and the gate drive is: p i 2 rms r ds(on) v gs t j d q g v gs v gs f ( watts ) eq1 [ ] the value of the parameter before the parenthesis is dependent on the parameter within the parenthesis. figure 1. generic mosfet model with body diode omitted. gate r g ciss crss i rms c oss r ds(on) source drain where: i 2 rms the rms current in the mosfet (a) r ds(on) on-resistance of the device for a given drive voltage and junction temperature. v gs the peak driver gate voltage for the mosfet (v) [t j ] junction temperature of the mosfet d duty factor of the mosfet (ratio of on time to off time) q g total gate charge for the mosfet at a given gate voltage (c) f frequency of mosfet switching (hz) using equation 1 we can obtain a plot of power loss (gate loss + r ds(on) loss) as a function of gate voltage at varying switching frequencies (figure 2). [1] power loss (mw) figure 2. power loss for pwm optimized si6801 p-channel mosfet as a function of v gs and switching frequency. 0 1 2 3 4 5 6 7 40 30 20 10 0 si6801 power loss, qg, r ds v gs r gate charge (nc) v gs 0.8 0.6 0.4 0.2 0 ( ds(on) figure 3. gate losses and on-resistance losses for pwm optimized power mosfet (si6801dq) versus conventional (si6542dq) and low-threshold (si6552dq) power mosfets. 1 v gs 50 40 30 20 10 conduction + gate charge loss (mw) 2 3 4 5 6 7 technology comparison: 1 mhz power loss ) 40 30 20 10 0
AN805 vishay siliconix www.vishay.com faxback 408-970-5600 2 document number: 70649 january 1997 figure 2 shows the respective contribution of on-resistance and gate charge to overall losses for the p-channel si6801dq at three different switching frequencies. at low gate-source voltages, the r ds(on) of the mosfet is high and therefore on-resistance losses dominate. at higher gate-source voltages, on-resistance becomes almost a constant and the gate charge losses controlled by q g dominate. gate losses increase with the switching frequency, causing a narrowing in the optimum gate voltage. therefore, the optimum drive voltage will be at a level which is just enough to take the r ds(on) into its constant region, but no further. typically, this drive voltage is between 3 and 5 v, which is what most controller ics provide. figure 3 compares the power losses, at a switching frequency of 1 mhz, of vishay siliconix's pwm optimized si6801dq, a conventional power mosfet (si6542dq), and a low-threshold power mosfet (si6552dq). power losses for the pwm optimized mosfet at gate drives between 2.5 and 5.5 v are significantly lower than both conventional and low-threshold mosfets, making the optimized device the obvious choice for all switching applications. [7.] the pwm optimized mosfet in a real application the pwm optimized power mosfet is best viewed in the context of a real application. in the example used here, the si6801dq is paired with the si9160bq switching regulator ic to create a synchronous boost converter for cellular telephones with the following specifications: input voltage: 2.7 v to 5 v (single-cell lithium ion battery is 2.7 v to 4.2 v) output voltage: 5 v output current: 1 a maximum gate drive voltage: 4.5 v control scheme: constant frequency voltage mode control switching frequency: varied by rc value from 300 khz to 1.8 mhz all results shown are with v in = 3.6 v, v out = 5 v, i out = 600 ma, f = 1 mhz unless otherwise stated. figure 4. si9160 boost converter test circuit used to compare mosfet technologies. ml c4 10 f 13 si9160 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 c11 36 pf r6 12 k c3 r3 d r v dd v s nc d max /ss d s comp p gnd fb ni v ref uvlo set c osc r osc gnd enable c2 0.1 f c10 0.1 f r5 100 k c5 0.1 f r1 10 k c4 0.1 f c6 22 pf r4 2.2 k c10 0.33 f 5 6 7 8 2 3 4 1 s 2 d 1 d 2 s 1 s 1 s 2 g 1 g 2 c8 5600 pf r9 100 r10 3.6 k r11 1.2 k c9 0.1 f ml c3 10 f ml c1 10 f d1 ls4148 d2 ls4148 ml c2 10 f 4.7 h si6801 0.1 f 2.2 k r2, 270 sync 1-cell liion 7. neither figure 2 nor figure 3 is intended for exacting power loss calculations. these figures should only be used as a comparative measure for various mosfet technologies.
AN805 vishay siliconix document number: 70649 january 1997 www.vishay.com faxback 408-970-5600 3 the following complementary n- and p-channel mosfets, all little foot tssop-8 devices, represent the three technologies under test: pwm optimized mosfet si6801dq conventional mosfet si6542dq . . . . . . . . . . low-threshold mosfet si6552dq . . . . . . . . . . figure 4 shows test circuit used. pwm optimized mosfet performance reducing gate charge is one way in which pwm optimized mosfets cut power losses. in a real application, another component of power loss is crossover losses. these are also minimized by the pwm optimized power mosfet design, and are discussed in detail in appendix a. figure 5 shows oscillograms of the boost converter switching waveform using the three different types of power mosfets. the switching speeds are 4 ns for the si6801dq pwm optimized mosfet and 11 ns for the conventional mosfet. the si6801dq provides a nearly threefold improvement and thus lower losses. in addition to the increase in basic switching speed, notice that the pwm optimized mosfet does not exhibit a large characteristic step in the voltage waveform. this step is due to the feedback capacitance from drain to gate of the mosfet or amillero capacitance (c rss in figure 1) being charged when the drain voltage is lower than the gate voltage during a switching transition from an off state to an on state. effectively the gate voltage is astalledo while the miller capacitance is charged, and this is reflected in the voltage waveform from drain to source. this is obviously an unwanted characteristic and has largely been eliminated with pwm optimized mosfet technology. a final component that affects the switching speed of a mosfet is the effective gate resistance (r g in figure 1). the effective gate resistance defines how fast the mosfet capacitance can be charged. it is therefore one of the dominant factors in determining how fast a mosfet will switch. vishay siliconix's pwm optimized mosfets provide a minimum effective gate resistance.
AN805 vishay siliconix www.vishay.com faxback 408-970-5600 4 document number: 70649 january 1997
figure 5. switching speed comparison between high-frequency, conventional, and low-threshold power mosfets. n-channel turn on 5 ns/dv high-frequency mosfet technology conventional mosfet technology low-threshold mosfet technology n-channel turn off 5 ns/dv si6801 si6542 si6552 si6801 si6542 si6552 4 ns 11 ns 14 ns 3 ns 11 ns 10 ns
AN805 vishay siliconix document number: 70649 january 1997 www.vishay.com faxback 408-970-5600 5 a power mosfet is made up of many single mosfet cells arranged in a parallel combination. in an ideal mosfet all the cells will turn on together when activated by a gate signal, and a minimum switching time transition will be obtained. this does not happen in a conventional mosfet layout because the gate signal has to propagate across the silicon in a turn-on awave,o where the cells nearest the gate bus turn on first with the outer cells following. the pwm optimized mosfet has symmetrical gate bussing, and its bonding and layout structures minimize the turn-on awave,o thus increasing the switching speed of the device. efficiency how much extra efficiency does the pwm optimized mosfet provide? a comparison of the efficiency of the synchronous boost converter (figure 4) using three different mosfet technologies shows that an improvement on the order of 5% can be made if an optimized device is used. figures 6, 7, and 8 show efficiency at switching frequencies ranging from 300 khz to 1.8 mhz, while figure 9 summarizes the efficiencies of the three technologies against switching frequency at an output current of 400 ma. for all the results shown, the input voltage for the synchronous boost converter was 3.6 v, with an output voltage of 5 v. the pwm optimized mosfet surpasses all other technologies while maintaining the highest efficiencies over the broadest load ranges at all switching frequencies. the conventional mosfet technology provides the same breadth of efficiency but at a reduced value. the low- threshold technology is clearly unsuited to switching at higher switching frequencies with a gate voltage of 4.5 v. as summarized in table 1, at all switching frequencies the pwm optimized mosfet technology gives superior performance, both in highest peak efficiencies and over the broadest load range, making it the ideal choice for most low-voltage dc-to-dc designs. figure 6. efficiency comparison between high-frequency, conventional, and low-threshold mosfets at a switching frequency of 300 khz. 100.00 % 90.00 80.00 70.00 60.00 200.0 400.0 0.0 800.0 1000.0 600.0 output current 0 to 1000 ma h % 6801 300 khz h % 6542 300 khz h % 6552 300 khz figure 7. efficiency comparison between high-frequency, conventional and low-threshold mosfets at a switching frequency of 300 khz 100.00 % 90.00 80.00 70.00 60.00 200.0 400.0 0.0 800.0 1000.0 600.0 output current 0 to 1000ma h % 6801 1 khz h % 6542 1 khz h % 6552 1 khz figure 8. efficiency comparison between high-frequency, conventional, and low-threshold mosfets at a switching frequency of 1.8 mhz. 100.00 % 90.00 80.00 70.00 60.00 200.0 400.0 0.0 800.0 1000.0 600.0 output current 0 to 1000ma h % 6801 1.8 mhz h % 6542 1.8 mhz h % 6552 1.8 mhz figure 9. efficiency vs. switching frequency comparing the pwm optimized mosfet technology with conventional and low-threshold technologies 500 1000 0 2000 1500 switching frequency (khz) 100 95 90 75 70 85 80 % h % 6801 400 ma h % 6542 400 ma h % 6552 400 ma
AN805 vishay siliconix www.vishay.com faxback 408-970-5600 6 document number: 70649 january 1997
type of mosfet typical on-resistance at 4.5 v (m ) specific gate charge normalized gate charge per 100 m (nc) pwm optimized 120 1.7 1.4 conventional 100 4.0 4.0 low- threshold 73 16.0 22.0 figure of merit for the pwm optimized mosfet technology normalized gate charge serves as a quick figure of merit for comparing the high-frequency, conventional, and low-threshold mosfets. this was calculated by normalizing the on-resistance and gate charge of the n-channel mosfet to 100 m : similar performance advantages will be seen for the p-channel process as well. application areas ideal applications for vishay siliconix's pwm optimized mosfets include mobile communication equipment and other hand-held battery-operated systems, where dc-to-dc converters are becoming essential, and any other application where small size and high efficiency are design criteria. a good example is the demonstration board used as an example in this application note. the si9160bq and si6801dq chip set is targeted for the cellular phone market where single-cell lithium ion batteries are becoming more popular and high-efficiency boost converters are required. the buck converter in notebook computers is another key application for vishay siliconix's pwm optimized mosfets. most buck converter controller ics today support synchronous operation and require all n-channel mosfets. a typical synchronous buck converter is shown in figure 10. in addition to non-isolated buck and boost topologies, vishay siliconix's pwm optimized mosfets are also very useful in the application of synchronous rectification for isolated converters (figure 11). the replacement of schottky diodes with mosfets on the output of isolated topologies is becoming more popular and even a necessity as output voltages drop below the 3-v level. this makes schottky diodes impractical for efficiency reasons. the biggest disadvantage to mosfets in isolated synchronous rectification is that mosfets have to be driven and schottkies don't. vishay siliconix's pwm optimized mosfets have a lower gate charge per unit ohm, making it a lot easier and more efficient to implement a given drive scheme. all n-channel or n- and p-control ic, eg., si9140, si9145 figure 10. all n-channel synchronous buck converter. figure 11. implementation for synchronous rectification in a resonant reset forward converter. conclusions vishay siliconix's pwm optimized mosfet technology goes beyond the traditional improvements in on-resistance that have been the standard benchmark for mosfets. this technology addresses gate, crossover and conduction losses giving the dc-to-dc converter designer several valuable advantages, including faster switching times, lower gate losses, and higher overall converter efficiency with a minimum footprint. references spice analysis of low loss control/power mosfet chip set for high frequency dc-dc converter design. jeff berwick, john huang, wayne grabowski and richard k. williams. siliconix inc. charles hymowitz and steve sandler. intusoft inc. hfpc power conversion, september 1996 proceedings. jerry fennel, ado cross talko, advance power supplies, bishop's stortford, england. andrew cowell, si9160 boost converter for mobile communications, may 1996.
AN805 vishay siliconix document number: 70649 january 1997 www.vishay.com faxback 408-970-5600 7
power loss due to crossover or switching transition loss can be calculated from the generic expression below p s f tts 1 v ds i d dt ts 2 v ds i d dt ts 1 ts 2 00 from this equation we can define the crossover losses generically for both resistive and clamped inductive loads. vds ids power dissipation v dd r l p = vds . ids (ts 1 + ts 2 ) f 6 vds ids power dissipation v dd r l p = vds (id 1 . ts 1 + id 2 . ts 2 ) f 2 resistive cross over losses clamped inductive cross over losses ts 1 ts 2 ts 1 ts 2 + v dd / r l ts 2 id 1
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